Datasheet

32.6.1.52 PIO Parallel Capture Interrupt Disable Register
Name: PIO_PCIDR
Offset: 0x0158
Property: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect
1: Disables the corresponding interrupt
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
RXBUFF ENDRX OVRE DRDY
Access
Reset
Bit 3 – RXBUFF Reception Buf
fer Full Interrupt Disable
Bit 2 – ENDRX End of Reception Transfer Interrupt Disable
Bit 1 – OVRE Parallel Capture Mode Overrun Error Interrupt Disable
Bit 0 – DRDY Parallel Capture Mode Data Ready Interrupt Disable
SAM E70/S70/V70/V71 Family
Parallel Input/Output Controller (PIO)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 378