Datasheet

32.6.1.50 PIO Parallel Capture Mode Register
Name: PIO_PCMR
Offset: 0x0150
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the PIO W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
FRSTS HALFS ALWYS
Access
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
DSIZE[1:0] PCEN
Access
Reset 0 0 0
Bit 11 – FRSTS Parallel Capture Mode First Sample
This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received with an
index from 0 to n:
Value Description
0
Only data with an even index are sampled.
1
Only data with an odd index are sampled.
Bit 10 – HALFS Parallel Capture Mode Half Sampling
Independently from the AL
WYS bit:
Value Description
0
The Parallel Capture mode samples all the data.
1
The Parallel Capture mode samples the data only every other time.
Bit 9 – ALWYS Parallel Capture Mode Always Sampling
Value Description
0
The Parallel Capture mode samples the data when both data enables are active.
1
The Parallel Capture mode samples the data whatever the data enables are.
Bits 5:4 – DSIZE[1:0] Parallel Capture Mode Data Size
Value Name Description
0
BYTE The reception data in the PIO_PCRHR is a byte (8-bit)
1
HALF-WORD The reception data in the PIO_PCRHR is a half-word (16-bit)
2
WORD The reception data in the PIO_PCRHR is a word (32-bit)
3
Reserved Reserved
Bit 0 – PCEN Parallel Capture Mode Enable
Value Description
0
The Parallel Capture mode is disabled.
SAM E70/S70/V70/V71 Family
Parallel Input/Output Controller (PIO)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 375