Datasheet

...........continued
LQFP Pin LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail I/O Type Primary Alternate PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir,
PU, PD,
HiZ, ST
84 H10 J12 VDDIO GPIO_AD PD14 I/O – – GRXCK I – – SDCKE O – – PIO, I, PU,
ST
106 A11 D11 VDDIO GPIO_AD PD15 I/O – – GTX2 O RXD2 I NWR1/N
BS1
O – – PIO, I, PU,
ST
78 K11 K10 VDDIO GPIO_AD PD16 I/O – – GTX3 O TXD2 I/O RAS O – – PIO, I, PU,
ST
74 L11 M13 VDDIO GPIO_AD PD17 I/O – – GTXER O SCK2 I/O CAS O – – PIO, I, PU,
ST
69 M10 M11 VDDIO GPIO_AD PD18 I/O – – NCS1/SD
CS
O RTS2 O URXD4 I – – PIO, I, PU,
ST
67 M9 L10 VDDIO GPIO_AD PD19 I/O – – NCS3 O CTS2 I UTXD4 O – – PIO, I, PU,
ST
65 K9 K9 VDDIO GPIO PD20 I/O – – PWMC0_
PWMH0
O SPI0_MIS
O
I/O GTSUCO
MP
O – – PIO, I, PU,
ST
63 H9 L9 VDDIO GPIO_AD PD21 I/O – – PWMC0_
PWMH1
O SPI0_MO
SI
I/O TIOA11 I/O ISI_D1 I PIO, I, PU,
ST
60 M8 N9 VDDIO GPIO_AD PD22 I/O – – PWMC0_
PWMH2
O SPI0_SP
CK
O TIOB11 I/O ISI_D0 I PIO, I, PU,
ST
57 M7 N7 VDDIO GPIO_CL
K
PD23 I/O – – PWMC0_
PWMH3
O – – SDCK O – – PIO, I, PU,
ST
55 M6 K7 VDDIO GPIO_AD PD24 I/O – – PWMC0_
PWML0
O RF I/O TCLK11 I ISI_HSYN
C
I PIO, I, PU,
ST
52 M5 L6 VDDIO GPIO_AD PD25 I/O – – PWMC0_
PWML1
O SPI0_NP
CS1
I/O URXD2 I ISI_VSYN
C
I PIO, I, PU,
ST
53 L6 M7 VDDIO GPIO PD26 I/O – – PWMC0_
PWML2
O TD O UTXD2 O UTXD1 O PIO, I, PU,
ST
47 J6 M5 VDDIO GPIO_AD PD27 I/O – – PWMC0_
PWML3
O SPI0_NP
CS3
O TWD2 O ISI_D8 I PIO, I, PU,
ST
71 K10 M12 VDDIO GPIO_AD PD28 I/O WKUP5
(1)
I URXD3 I - I TWCK2 O ISI_D9 I PIO, I, PU,
ST
108 D10 B13 VDDIO GPIO_AD PD29 I/O – – – – – – SDWE O – – PIO, I, PU,
ST
34 M1 L2 VDDIO GPIO_AD PD30 I/O AFE0_AD
0
(5)
I UTXD3 O – – – – ISI_D10 I PIO, I, PU,
ST
2 D3 C3 VDDIO GPIO_AD PD31 I/O – – QIO3 I/O UTXD3 O PCK2 O ISI_D11 I PIO, I, PU,
ST
4 C2 C2 VDDIO GPIO_AD PE0 I/O AFE1_AD
1
1
(5)
I D8 I/O TIOA9 I/O I2SC1_W
S
I/O – – PIO, I, PU,
ST
6 A1 D2 VDDIO GPIO_AD PE1 I/O – – D9 I/O TIOB9 I/O I2SC1_D O O – – PIO, I, PU,
ST
7 B1 D1 VDDIO GPIO_AD PE2 I/O – – D10 I/O TCLK9 I I2SC1_DI I – – PIO, I, PU,
ST
10 E3 F1 VDDIO GPIO_AD PE3 I/O AFE1_AD
10
(5)
I D11 I/O TIOA10 I/O – – – – PIO, I, PU,
ST
27 K1 K2 VDDIO GPIO_AD PE4 I/O AFE0_AD
4
(5)
I D12 I/O TIOB10 I/O – – – – PIO, I, PU,
ST
28 L1 K3 VDDIO GPIO_AD PE5 I/O AFE0_AD
3
(5)
I D13 I/O TCLK10 I/O – – – – PIO, I, PU,
ST
3 C3 E4 VDDOUT Power VDDOUT – – – – – – – – – – – –
5 C1 C1 VDDIN Power VDDIN – – – – – – – – – – – –
8 D2 E2 GND Reference VREFN I – – – – – – – – – – –
9 D1 E1 VDDIO Reference VREFP I – – – – – – – – – – –
83 H12 K12 VDDIO RST NRST I/O – – – – – – – – – – I, PU
85 H11 J13 VDDIO TEST TST I – – – – – – – – – – I, PD
30,43,72,8
0,96
G8,H6,H7 D6,F10,K6 VDDIO Power VDDIO – – – – – – – – – – – –
104 B11 D12 VDDIO TEST JTAGSEL I – – – – – – – – – – I, PD
SAM E70/S70/V70/V71 Family
Package and Pinout
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 34