Datasheet

...........continued
Offset Name Bit Pos.
0x0100 PIO_SCHMITT
7:0 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0
15:8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8
23:16 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16
31:24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24
0x0104
...
0x01
17
Reserved
0x0118 PIO_DRIVER1
7:0 LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0
15:8 LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8
23:16 LINE23 LINE22 LINE21 LINE20 LINE19 LINE18 LINE17 LINE16
31:24 LINE31 LINE30 LINE29 LINE28 LINE27 LINE26 LINE25 LINE24
0x011C
...
0x014F
Reserved
0x0150 PIO_PCMR
7:0 DSIZE[1:0] PCEN
15:8 FRSTS HALFS ALWYS
23:16
31:24
0x0154 PIO_PCIER
7:0 RXBUFF ENDRX OVRE DRDY
15:8
23:16
31:24
0x0158 PIO_PCIDR
7:0 RXBUFF ENDRX OVRE DRDY
15:8
23:16
31:24
0x015C PIO_PCIMR
7:0 RXBUFF ENDRX OVRE DRDY
15:8
23:16
31:24
0x0160 PIO_PCISR
7:0 OVRE DRDY
15:8
23:16
31:24
0x0164 PIO_PCRHR
7:0 RDATA[7:0]
15:8 RDATA[15:8]
23:16 RDATA[23:16]
31:24 RDATA[31:24]
32.6.1 Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface
registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no
ef
fect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the
PIO Controller and PIO_PSR returns one systematically.
SAM E70/S70/V70/V71 Family
Parallel Input/Output Controller (PIO)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 325