Datasheet

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PIO_PPDER 0x00F0_0000

PIO_ABCDSR1 0xF0F0_0000

PIO_ABCDSR2 0xFF00_0000

PIO_OWER 0x0000_000F

PIO_OWDR 0x0FFF_FFF0

32.5.16 Register Write Protection

To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be

write-protected by setting the WPEN bit in the PIO W

rite Protection Mode Register (PIO_WPMR).

If a write access to a write-protected register is detected, the WPVS flag in the PIO Write Protection Status Register

(PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.

The WPVS bit is automatically cleared after reading the PIO_WPSR.

The following registers can be write-protected:

• PIO Enable Register

• PIO Disable Register

• PIO Output Enable Register

• PIO Output Disable Register

• PIO Input Filter Enable Register

• PIO Input Filter Disable Register

• PIO Multi-driver Enable Register

• PIO Multi-driver Disable Register

• PIO Pull-Up Disable Register

• PIO Pull-Up Enable Register

• PIO Peripheral ABCD Select Register 1

• PIO Peripheral ABCD Select Register 2

• PIO Output Write Enable Register

• PIO Output Write Disable Register

• PIO Pad Pull-Down Disable Register

• PIO Pad Pull-Down Enable Register

• PIO Parallel Capture Mode Register

SAM E70/S70/V70/V71 Family

Parallel Input/Output Controller (PIO)

echnology Inc.

Datasheet

DS60001527D-page 320