Datasheet

...........continued
LQFP Pin LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail I/O Type Primary Alternate PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir,
PU, PD,
HiZ, ST
21 H4 H2 VDDIO GPIO PB0 I/O AFE0_AD1
0/
R
TCOUT
0
(7)
I PWMC0_
PWMH0
O – – RXD0 I TF I/O PIO, I, PU,
ST
20 G3 H1 VDDIO GPIO PB1 I/O AFE1_AD0
/ RTCOUT
1
(7)
I PWMC0_
PWMH1
O GTSUCO
MP
O TXD0 I/O TK I/O PIO, I, PU,
ST
26 J2 K1 VDDIO GPIO PB2 I/O AFE0_AD5
(5)
I CANTX0 O – – CTS0 I SPI0_NP
CS0
I/O PIO, I, PU,
ST
31 J3 L1 VDDIO GPIO_AD PB3 I/O AFE0_AD2
/
WKUP12
(6
)
I CANRX0 I PCK2 O RTS0 O ISI_D2 I PIO, I, PU,
ST
105 A12 C13 VDDIO GPIO_ML
B
PB4 I/O TDI
(9)
I TWD1 I/O PWMC0_
PWMH2
O MLBCLK I TXD1 I/O PIO, I, PU,
ST
109 C10 C12 VDDIO GPIO_ML
B
PB5 I/O TDO/TRA
CESWO/
WKUP13
(9
)
O TWCK1 O PWMC0_
PWML0
O MLBDAT I/O TD O O, PU
79 J11 K11 VDDIO GPIO PB6 I/O SWDIO/T
MS
(9)
I – – – – – – – – PIO,I,ST
89 F9 H13 VDDIO GPIO PB7 I/O SWCLK/TC
K
(9)
I – – – – – – – – PIO,I,ST
141 A3 B2 VDDIO CLOCK PB8 I/O XOUT
(10)
O – – – – – – – – PIO, HiZ
142 A2 A2 VDDIO CLOCK PB9 I/O XIN
(10)
I – – – – – – – – PIO, HiZ
87 G12 J10 VDDIO GPIO PB12 I/O ERASE
(9)
I PWMC0_
PWML1
O GTSUCO
MP
O – – PCK0 O PIO, I, PD,
ST
144 B2 A1 VDDIO GPIO_AD PB13 I/O DAC0
(11)
O PWMC0_
PWML2
O PCK0 O SCK0 I/O – – PIO, I, PU,
ST
11 E4 F2 VDDIO GPIO_AD PC0 I/O AFE1_AD9
(5)
I D0 I/O PWMC0_
PWML0
O – – – – PIO, I, PU,
ST
38 J4 M3 VDDIO GPIO_AD PC1 I/O – – D1 I/O PWMC0_
PWML1
O – – – – PIO, I, PU,
ST
39 K4 N3 VDDIO GPIO_AD PC2 I/O – – D2 I/O PWMC0_
PWML2
O – – – – PIO, I, PU,
ST
40 L3 N4 VDDIO GPIO_AD PC3 I/O – – D3 I/O PWMC0_
PWML3
O – – – – PIO, I, PU,
ST
41 J5 L3 VDDIO GPIO_AD PC4 I/O – – D4 I/O – – – – – – PIO, I, PU,
ST
58 L8 M8 VDDIO GPIO_AD PC5 I/O – – D5 I/O TIOA6 I/O – – – – PIO, I, PU,
ST
54 K7 L7 VDDIO GPIO_AD PC6 I/O – – D6 I/O TIOB6 I/O – – – – PIO, I, PU,
ST
48 M4 L5 VDDIO GPIO_AD PC7 I/O – – D7 I/O TCLK6 I – – – – PIO, I, PU,
ST
82 J12 K13 VDDIO GPIO_AD PC8 I/O – – NWR0/N
WE
O TIOA7 I/O – – – – PIO, I, PU,
ST
86 G11 J11 VDDIO GPIO_AD PC9 I/O – – NANDOE O TIOB7 I/O – – – – PIO, I, PU,
ST
90 F10 H12 VDDIO GPIO_AD PC10 I/O – – NANDWE O TCLK7 I – – – – PIO, I, PU,
ST
94 F11 F13 VDDIO GPIO_AD PC11 I/O – – NRD O TIOA8 I/O – – – – PIO, I, PU,
ST
17 F4 G2 VDDIO GPIO_AD PC12 I/O AFE1_AD3
(5)
I NCS3 O TIOB8 I/O CANRX1 I – – PIO, I, PU,
ST
19 G2 H3 VDDIO GPIO_AD PC13 I/O AFE1_AD1
(5)
I NWAIT I PWMC0_
PWMH3
O SDA10 O – – PIO, I, PU,
ST
97 E10 F12 VDDIO GPIO_AD PC14 I/O – – NCS0 O TCLK8 I CANTX1 O – – PIO, I, PU,
ST
18 G1 H4 VDDIO GPIO_AD PC15 I/O AFE1_AD2
(5)
I NCS1/SD
CS
O PWMC0_
PWML3
O – – – – PIO, I, PU,
ST
SAM E70/S70/V70/V71 Family
Package and Pinout
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 32