Datasheet

32.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The
Input Edge/Level interrupt is controlled by writing the Interrupt Enable Register (PIO_IER) and the Interrupt Disable
Register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and clearing the
corresponding bit in the Interrupt Mask Register (PIO_IMR). As input change detection is possible only by comparing
two successive samplings of the input of the I/O line, the peripheral clock must be enabled. The Input Change
interrupt is available regardless of the configuration of the I/O line, i.e., configured as an input only
, controlled by the
PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable
Register (PIO_AIMER) and Additional Interrupt Modes Disable Register (PIO_AIMDR). The current state of this
selection can be read through the Additional Interrupt Modes Mask Register (PIO_AIMMR).
These additional modes are:
• Rising edge detection
• Falling edge detection
• Low-level detection
• High-level detection
In order to select an additional interrupt mode:
• The type of event detection (edge or level) must be selected by writing in the Edge Select Register (PIO_ESR)
and Level Select Register (PIO_LSR) which select, respectively, the edge and level detection. The current status
of this selection is accessible through the Edge/Level Status Register (PIO_ELSR).
• The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the Falling
Edge/Low-Level Select Register (PIO_FELLSR) and Rising Edge/High-Level Select Register (PIO_REHLSR)
which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high- or low-level detection
(if level is selected in PIO_ELSR). The current status of this selection is accessible through the Fall/Rise - Low/
High Status Register (PIO_FRLHSR).
When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status Register
(PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The interrupt
signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts
that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
Figure 32-6. Event Detector on Input Lines (Figure Represents Line 0)
Event Detector
0
1
0
1
1
0
0
1
Edge
Detector
Falling Edge
Detector
Rising Edge
Detector
PIO_FELLSR[0]
PIO_FRLHSR[0]
PIO_REHLSR[0]
Low Level
Detector
High Level
Detector
PIO_ESR[0]
PIO_ELSR[0]
PIO_LSR[0]
PIO_AIMDR[0]
PIO_AIMMR[0]
PIO_AIMER[0]
Event detection on line 0
Resynchronized input on line 0
Example of interrupt generation on following lines:
SAM E70/S70/V70/V71 Family
Parallel Input/Output Controller (PIO)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 314