Datasheet

The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock
Disable Register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable Register (PIO_IFSCER). W
riting
PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status Register
(PIO_IFSCSR).
The current selection status can be checked by reading the PIO_IFSCSR.
• If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period.
• If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable
divided slow clock period.
For the debouncing filter, the period of the divided slow clock is defined by writing in the DIV field of the Slow Clock
Divider Debouncing Register (PIO_SCDR):
t
div_slck
= ((DIV + 1) × 2) × t
slck
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle
(selected clock represents peripheral clock or divided slow clock depending on PIO_IFSCDR and PIO_IFSCER
programming) is automatically rejected, while a pulse with a duration of one selected clock (peripheral clock or
divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock cycle and one selected
clock cycle, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus
for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch to be reliably filtered out, its
duration must not exceed 1/2 selected clock cycle.
The filters also introduce some latencies, illustrated in the following two figures.
The glitch filters are controlled by the Input Filter Enable Register (PIO_IFER), the Input Filter Disable Register
(PIO_IFDR) and the Input Filter Status Register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets and
clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It
acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing
filters require that the peripheral clock is enabled.
Figure 32-4. Input Glitch Filter Timing
Peripheral clcok
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle 1 cycle 1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles
up to 2 cycles
1 cycle
1 cycle
PIO_IFCSR = 0
Figure 32-5. Input Debouncing Filter Timing
Divided Slow Clock
(div_slck)
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle t
div_slck
up to 1.5 cycles t
div_slck
1 cycle t
div_slck
up to 2 cycles t
peripheral clock
up to 2 cycles t
peripheral clock
up to 2 cycles t
peripheral clock
up to 2 cycles t
peripheral clock
up to 1.5 cycles t
div_slck
PIO_IFCSR = 1
SAM E70/S70/V70/V71 Family
Parallel Input/Output Controller (PIO)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 313