Datasheet

Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level
driven on the I/O line.
32.5.5 Synchronous Data Output
Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by using
PIO_SODR and PIO_CODR. It requires two successive write operations into two dif
ferent registers. To overcome
this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only bits
unmasked by the Output Write Status Register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set by
writing to the Output Write Enable Register (PIO_OWER) and cleared by writing to the Output Write Disable Register
(PIO_OWDR).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
32.5.6 Multi-Drive Control (Open Drain)
Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits
several drivers to be connected on the I/O line which is driven low only by each device. An external pullup resistor (or
enabling of the internal one) is generally required to guarantee a high level on the line.
The multi-drive feature is controlled by the Multi-driver Enable Register (PIO_MDER) and the Multi-driver Disable
Register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or
assigned to a peripheral function. The Multi-driver Status Register (PIO_MDSR) indicates the pins that are configured
to support external drivers.
After reset, the multi-drive feature is disabled on all pins, i.e., PIO_MDSR resets at value 0x0.
32.5.7 Output Line Timings
The following figure shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly
writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. The Output Line T
imings
figure also shows when the feedback in the Pin Data Status Register (PIO_PDSR) is available.
Figure 32-3. Output Line Timings
2 cycles
APB Access
2 cycles
APB Access
Peripheral clock
Write PIO_SODR
Write PIO_ODSR at 1
PIO_ODSR
PIO_PDSR
Write PIO_CODR
Write PIO_ODSR at 0
32.5.8 Inputs
The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless
of their configuration, whether uniquely as an input, or driven by the PIO Controller
, or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the
levels present on the I/O line at the time the clock was disabled.
32.5.9 Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock and the debouncing filter can filter a
pulse of less than 1/2 period of a programmable divided slow clock.
SAM E70/S70/V70/V71 Family
Parallel Input/Output Controller (PIO)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 312