Datasheet

32.5.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable Register
(PIO_PER) and the Disable Register (PIO_PDR). The Status Register (PIO_PSR) is the result of the set and clear
registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller
. A value
of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the Peripheral ABCD
Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO
Controller.
If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR
have no effect and PIO_PSR returns a one for the corresponding bit.
After reset, the I/O lines are controlled by the PIO Controller, i.e., PIO_PSR resets at one. However, in some events,
it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be
driven inactive after reset, or for address lines that must be driven low for booting out of an external memory). Thus,
the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the device.
32.5.3 Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed
by writing PIO_ABCDSR1 and PIO_ABCDSR2.
For each pin:
•
The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2
means peripheral A is selected.
• The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2
means peripheral B is selected.
• The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2
means peripheral C is selected.
• The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2
means peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are
always connected to the pin input (refer to Figure 32-2).
Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin.
However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2 in
addition to a write in PIO_PDR.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on
peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O Line mode.
If the software selects a peripheral A, B, C or D which does not exist for a pin, no alternate functions are enabled for
this pin and the selection is taken into account. The PIO Controller does not carry out checks to prevent selection of a
peripheral which does not exist.
32.5.4 Output Control
When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of
the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and
PIO_ABCDSR2 determines whether the pin is driven or not.
When the I/O line is controlled by the PIO Controller
, the pin can be configured to be driven. This is done by writing
the Output Enable Register (PIO_OER) and Output Disable Register (PIO_ODR). The results of these write
operations are detected in the Output Status Register (PIO_OSR). When a bit in this register is at zero, the
corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the PIO
Controller.
The level driven on an I/O line can be determined by writing in the Set Output Data Register (PIO_SODR) and the
Clear Output Data Register (PIO_CODR). These write operations, respectively, set and clear the Output Data Status
Register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR
manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to a peripheral
function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller.
SAM E70/S70/V70/V71 Family
Parallel Input/Output Controller (PIO)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 311