Datasheet

6.1.2 144-ball LFBGA/TFBGA Package Outline
Figure 6-2. Orientation of the 144-ball LFBGA/TFBGA Package
6.1.3 144-ball UFBGA Package Outline
Figure 6-3. Orientation of the 144-ball UFBGA Package
6.2 144-lead Package Pinout
Table 6-1. 144-lead Package Pinout
LQFP Pin LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail I/O Type Primary Alternate PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir,
PU, PD,
HiZ, ST
102 C11 E11 VDDIO GPIO_AD PA0 I/O WKUP0
(1)
I PWMC0_
PWMH0
O TIOA0 I/O A17/BA1 O I2SC0_M
CK
O PIO, I, PU,
ST
99 D12 F11 VDDIO GPIO_AD PA1 I/O WKUP1
(1)
I PWMC0_
PWML0
O TIOB0 I/O A18 O I2SC0_C K I/O PIO, I, PU,
ST
93 E12 G12 VDDIO GPIO PA2 I/O WKUP2
(1)
I PWMC0_
PWMH1
O – – DATRG I – – PIO, I, PU,
ST
91 F12 G11 VDDIO GPIO_AD PA3 I/O PIODC0
(2)
I TWD0 I/O LONCOL 1 I PCK2 O – – PIO, I, PU,
ST
77 K12 L12 VDDIO GPIO PA4 I/O WKUP3/P
IODC1
(3)
I TWCK0 O TCLK0 I UTXD1 O – – PIO, I, PU,
ST
SAM E70/S70/V70/V71 Family
Package and Pinout
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 30