Datasheet

31.20.26 PMC Peripheral Control Register
Name: PMC_PCR
Offset: 0x010C
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
GCLKEN EN GCLKDIV[7:4]
Access
Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
GCLKDIV[3:0]
Access
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CMD GCLKCSS[2:0]
Access
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PID[6:0]
Access
Reset 0 0 0 0 0 0 0
Bit 29 – GCLKEN Generic Clock Enable
Value Description
0
The selected generic clock is disabled.
1
The selected generic clock is enabled.
Bit 28 – EN Enable
Value Description
0
Selected Peripheral clock is disabled.
1
Selected Peripheral clock is enabled.
Bits 27:20 – GCLKDIV[7:0] Generic Clock Division Ratio
Generic clock is the selected clock period divided by GCLKDIV + 1.
GCLKDIV must not be changed while the peripheral selects GCLKx (e.g., bit rate, etc.).
Bit 12 – CMD Command
Value Description
0
Read mode.
1
Write mode.
Bits 10:8 – GCLKCSS[2:0] Generic Clock Source Selection
Value Name Description
0
SLOW_CLK SLCK is selected
1
MAIN_CLK MAINCK is selected
2
PLLA_CLK PLLACK is selected
3
UPLL_CLK UPLLCK is selected
4
MCK_CLK MCK is selected
5
AUDIO_CLK AUDIOPLLCLK is selected
SAM E70/S70/V70/V71 Family
Power Management Controller (PMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 294