Datasheet

31.20.17 PMC Interrupt Mask Register
Name: PMC_IMR
Offset: 0x006C
Reset: 0x00000000
Property: Read-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Enables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
XT32KERR CFDEV MOSCRCS MOSCSELS
Access
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
LOCKU MCKRDY LOCKA MOSCXTS
Access
Reset 0 0 0 0
Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Mask
Bit 18 – CFDEV Clock Failure Detector Event Interrupt Mask
Bit 17 – MOSCRCS Main RC Status Interrupt Mask
Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Mask
Bits 8, 9, 10, 1
1, 12, 13, 14, 15 – PCKRDY Programmable Clock Ready x Interrupt Mask
Bit 6 – LOCKU UTMI PLL Lock Interrupt Mask
Bit 3 – MCKRDY Master Clock Ready Interrupt Mask
Bit 1 – LOCKA PLLA Lock Interrupt Mask
Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Mask
SAM E70/S70/V70/V71 Family
Power Management Controller (PMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 284