Datasheet

31.20.11 PMC Master Clock Register
Name: PMC_MCKR
Offset: 0x0030
Reset: 0x00000001
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC W
rite Protection Mode Register.
UPLLDIV2 UPLL Clock Division
0 UPLLCK frequency is divided by 1.
1 UPLLCK frequency is divided by 2.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
UPLLDIV2 MDIV[1:0]
Access
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
PRES[2:0] CSS[1:0]
Access
Reset 0 0 0 0 1
Bit 13 – UPLLDIV2 UPLL Divider by 2
Bits 9:8 – MDIV[1:0] Master Clock Division
Value Name Description
0
EQ_PCK MCK is FCLK divided by 1.
1
PCK_DIV2 MCK is FCLK divided by 2.
2
PCK_DIV4 MCK is FCLK divided by 4.
3
PCK_DIV3 MCK is FCLK divided by 3.
Bits 6:4 – PRES[2:0] Processor Clock Prescaler
Value Name Description
0
CLK_1 Selected clock
1
CLK_2 Selected clock divided by 2
2
CLK_4 Selected clock divided by 4
3
CLK_8 Selected clock divided by 8
4
CLK_16 Selected clock divided by 16
5
CLK_32 Selected clock divided by 32
6
CLK_64 Selected clock divided by 64
7
CLK_3 Selected clock divided by 3
Bits 1:0 – CSS[1:0] Master Clock Source Selection
SAM E70/S70/V70/V71 Family
Power Management Controller (PMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 276