Datasheet

31.20.7 PMC UTMI Clock Configuration Register
Name: CKGR_UCKR
Offset: 0x001C
Reset: 0x10200800
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
UPLLCOUNT[3:0] UPLLEN
Access
Reset 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
Access
Reset
Bits 23:20 – UPLLCOUNT[3:0] UTMI PLL Startup T
ime
Specifies the number of SLCK cycles multiplied by 8 for the UTMI PLL startup time.
Bit 16 – UPLLEN UTMI PLL Enable
When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
Value Description
0
The UTMI PLL is disabled.
1
The UTMI PLL is enabled.
SAM E70/S70/V70/V71 Family
Power Management Controller (PMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 271