Datasheet

7. Select MCK and HCLK:
MCK and HCLK are configurable via PMC_MCKR.
CSS is used to select the clock source of MCK and HCLK. By default, the selected clock source is MAINCK.
PRES is used to define the HCLK and MCK prescaler
.s The user can choose between different values (1, 2, 3,
4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value.
MDIV is used to define the MCK divider. It is possible to choose between different values (0, 1, 2, 3). MCK
output is the HCLK frequency divided by 1, 2, 3 or 4, depending on the value programmed in MDIV.
By default, MDIV is cleared, which indicates that the HCLK is equal to MCK.
Once the PMC_MCKR has been written, the user must wait for PMC_SR.MCKRDY to be set. This can be
done either by polling PMC_SR.MCKRDY or by waiting for the interrupt line to be raised if the associated
interrupt source (MCKRDY) has been enabled in PMC_IER. PMC_MCKR must not be programmed in a single
write operation. The programming sequence for PMC_MCKR is as follows:
If a new value for PMC_MCKR.CSS corresponds to any of the available PLL clocks:
a. Program PMC_MCKR.PRES.
b. Wait for PMC_SR.MCKRDY to be set.
c. Program PMC_MCKR.MDIV.
d. Wait for PMC_SR.MCKRDY to be set.
e. Program PMC_MCKR.CSS.
f. Wait for PMC_SR.MCKRDY to be set.
If a new value for PMC_MCKR.CSS corresponds to MAINCK or SLCK:
a. Program PMC_MCKR.CSS.
b. Wait for PMC_SR.MCKRDY to be set.
c. Program PMC_MCKR.PRES.
d. Wait for PMC_SR.MCKRDY to be set.
If CSS, MDIV or PRES are modified at any stage, the MCKRDY bit goes low to indicate that MCK and HCLK
are not yet ready. The user must wait for MCKRDY bit to be set again before using MCK and HCLK.
Note: If PLLA clock was selected as MCK and the user decides to modify it by writing a new value into
CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCKA
goes high and MCKRDY is set.
While PLLA is unlocked, MCK selection is automatically changed to SLCK for PLLA. For further information,
see "Clock Switching Waveforms".
MCK is MAINCK divided by 2.
8. Select the Programmable clocks (PCKx):
PCKx are controlled via registers PMC_SCER, PMC_SCDR and PMC_SCSR.
PCKx can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Three PCKx can be used.
PMC_SCSR indicates which PCKx is enabled. By default all PCKx are disabled.
PMC_PCKx registers are used to configure PCKx.
PMC_PCKx.CSS is used to select the PCKx divider source. Several clock options are available:
– MAINCK
– SLCK
– MCK
– PLLACK
– UPLLCKDIV
SLCK is the default clock source.
SAM E70/S70/V70/V71 Family
Power Management Controller (PMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 259