Datasheet

The failure detector can be enabled or disabled by configuring the CKGR_MOR.CFDEN, and it can also be disabled
in either of the following cases:
•
After a VDDCORE reset
• When the Main crystal oscillator is disabled (MOSCXTEN = 0)
A failure is detected by means of a counter incrementing on the Main crystal oscillator output and detection logic is
triggered by the Slow RC oscillator which is automatically enabled when CFDEN = 1.
The counter is cleared when the Slow RC oscillator clock signal is low and enabled when the signal is high. Thus, the
failure detection time is one Slow RC oscillator period. If, during the high level period of the Slow RC oscillator clock
signal, less than eight Main crystal oscillator clock periods have been counted, then a failure is reported. Note that
when enabling the failure detector, up to two cycles of the Slow RC oscillator are needed to detect a failure of the
Main crystal oscillator.
If a failure of Main crystal oscillator is detected, PMC_SR.CFDEV and PMC_SR.FOS both indicate a failure event.
PMC_SR.CFDEV is cleared on read of PMC_SR, and PMC_SR.FOS is cleared by writing a ‘1’ to the FOCLR bit in
the PMC Fault Output Clear Register (PMC_FOCR).
Only PMC_SR.CFDEV can generate an interrupt if the corresponding interrupt source is enabled in PMC_IER. The
current status of the clock failure detection can be read at any time from PMC_SR.CFDS.
Figure 31-5. Clock Failure Detection Example
Main Crystal Oscillator Output
Slow
Clock
Note: Ratio of clock periods is for illustration purposes only.
CFDEV
CFDS
Read PMC_SR
If the Main crystal oscillator is selected as the source clock of MAINCK (CKGR_MOR.MOSCSEL = 1), and if the MCK
source is PLLACK or UPLLCKDIV (CSS = 2 or 3), a clock failure detection automatically forces MAINCK to be the
source clock for MCK. Then, regardless of the PMC configuration, a clock failure detection automatically forces the
Main RC oscillator to be the source clock for MAINCK. If the Main RC oscillator is disabled when a clock failure
detection occurs, it is automatically re-enabled by the clock failure detection mechanism.
T
wo Slow RC oscillator clock cycles are necessary to detect and switch from the Main crystal oscillator to the Main
RC oscillator if the source of MCK is MAINCK, or three Slow RC oscillator clock cycles if the source of MCK is
PLLACK or UPLLCKDIV.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller.
With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock failure
is detected.
31.16 32.768 kHz Crystal Oscillator Frequency Monitor
The frequency of the 32.768 kHz crystal oscillator can be monitored by means of logic driven by the Main RC
oscillator known as a reliable clock source. This function is enabled by configuring the XT32KFME bit of
CKGR_MOR. Prior to enabling this frequency monitor
, the 32.768 kHz crystal oscillator must be started and its
startup time be elapsed. Refer to details on the Slow clock generator in the section “Supply Controller (SUPC)”.
An error flag (XT32KERR in PMC_SR) is asserted when the 32.768 kHz crystal oscillator frequency is out of the
±10% nominal frequency value (i.e., 32.768 kHz). The error flag can be cleared only if the frequency monitor is
disabled.
When the Main RC oscillator frequency is set to 4 MHz, the accuracy of the measurement is ±40% as this frequency
is not trimmed during production. Therefore, ±10% accuracy is obtained only if the Main RC oscillator frequency is
configured for 8 or 12 MHz.
SAM E70/S70/V70/V71 Family
Power Management Controller (PMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 257