Datasheet

Refer to the section “ARM Cortex-M7 Processor” for details on selecting the SysTick external clock.
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15. ARM Cortex-M7 (ARM)
31.7 USB Full-speed Clock Controller
The user can select the PLLA or the UPLL output as the USB FS clock (USB_48M) by writing a ‘1’ to the USBS bit in
the USB Clock Register (PMC_USB). The user then must program the corresponding PLL to generate an appropriate
frequency depending on the USBDIV bit in PMC_USB.
When PMC_SR.LOCKA and PMC_SR.LOCKU are set to ‘1’, the PLLA and UPLL are stable. Then, USB_48M can be
enabled by setting the USBCLK bit in the System Clock Enable register (PMC_SCER). T
o save power on this
peripheral when not used, the user can set the USBCLK bit in the System Clock Disable register (PMC_SCDR). The
USBCLK bit in the System Clock Status register (PMC_SCSR) gives the status of this clock. The USB port requires
both the USB clock signal and the peripheral clock. The USB peripheral clock is controlled by means of the Master
Clock Controller.
31.8 Core and Bus Independent Clocks for Peripherals
The following table lists the peripherals that require a PCKx clock to operate while the core, bus and peripheral clock
frequencies are modified, thus providing communications at a bit rate which is independent for the core/bus/
peripheral clock. This mode of operation is possible by using the internally generated independent clock sources.
Internal clocks can be independently selected between SLCK, MAINCK, any available PLL clock, and MCK by
configuring PMC_PCKx.CSS. The independent clock sources can be also divided by configuring PMC_PCKx.PRES.
Each internal clock signal (PCKx) can be enabled and disabled by writing a ‘1’ to the corresponding
PMC_SCER.PCKx and PMC_SCDR.PCKx, respectively
. The status of the internal clocks are given in
PMC_SCSR.PCKx.
The status flag PMC_SR.PCKRDYx indicates that the programmable internal clock has been programmed in the
Programmable clock registers.
The independent clock source must also be selected in each peripheral in the Clock Assignments table to operate
communications, timings, etc without influencing the frequency of the core/bus/peripherals (except frequency
limitations listed in each peripheral).
Table 31-1. Clock Assignments
Clock Name Peripheral
PCK3 ETM
PCK4 UARTx/USARTx
PCK5 MCANx
PCK6 TCx
PCK7 TC0
Note: USB, GMAC and MLB do not require PCKx to operate independently of core and bus peripherals.
31.9 Peripheral and Generic Clock Controller
The PMC controls the clocks of the embedded peripherals by means of the Peripheral Control register (PMC_PCR).
With this register
, the user can enable and disable the different clocks used by the peripherals:
• Peripheral clocks (periph_clk[PID]), routed to every peripheral and derived from the master clock (MCK), and
• Generic clocks (GCLK[PID]), routed to I2SC0 and I2SC1. These clocks are independent of the core and bus
clocks (HCLK, MCK and periph_clk[PID]). They are generated by selection and division of the following sources:
SAM E70/S70/V70/V71 Family
Power Management Controller (PMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 252