Datasheet

31.3 Block Diagram
Figure 31-1. General Clock Distribution Block Diagram
Power
Management
Controller
User Interface
ControlStatus
Main
Crystal
Oscillator
PLLA
XIN
XOUT
XIN32
XOUT32
Slow RC
Oscillator
0
1
0
1
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/3,/4,/8,
/16,/32,/64
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
(PMC_MCKR)
Prescaler
PCK[..]
(to I/O pins
and
peripherals)
SysTick External Clock
Divider
/2
SLCK
MAINCK
PLLACK
USB UTMI
PLL
Main RC
Oscillator
Programmable Clock Controller
(PMC_PCKx)
PRES
PRES
CSS
CSS
Divider
/1, /2
UPLLDIV2
Divider
/1,/2,/3,...,/16
USB Clock Controller (PMC_USB)
USBDIVUSBS
UPLLCKDIV
PLLACK
MCK
Slow Clock (SLCK)
Clock Generator
SUPC_CR.XTALSEL
PMC_MCKR
MOSCSEL
CKGR_MOR
(PMC_SCER/SCDR)
/1 to /256
granularity=1
/1, /2, /3, /4
Divider
MDIV
periph_clk[PID]
(to peripherals)
Peripheral
Clock Controller
(PMC_PCR)
EN(PID)
PCKx
USBCLK
UPLLCKDIV
UPLLCKDIV
MCK
PLLACK
UPLLCKDIV
MAINCK
SLCK
GCLKCSS(PID)
Prescaler
/1,/2,/3,...,/256
GCLKDIV(PID)
GCLK[PID]
(to peripherals)
GCLKEN(PID)
32.768 kHz
Crystal
Oscillator
Main Clock (MAINCK)
PLLA Clock (PLLACK)
UPLL Clock (UPLLCK)
USB FS Clock (USB_48M)
Processor Clock (HCLK)
Free Running Clock (FCLK)
Master Clock (MCK)
USB HS Clock (USB_480M)
31.4 Master Clock Controller
The Master Clock Controller provides the Master Clock (MCK) with the selection and division of the clock generator's
output signals. MCK is the source clock of the peripheral clocks.
The clock to be selected between SLCK, MAINCK, PLLACK and UPLLCKDIV is configured in PMC_MCKR.CSS.
The prescaler supports the 1, 2, 3, 4, 8, 16, 32, 64 division factors and is configured using PMC_MCKR.PRES.
Each time PMC_MCKR is configured to define a new MCK, the MCKRDY bit is cleared in PMC_SR. It reads ‘0’ until
MCK is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor
. This feature is useful
when switching from a high-speed clock to a lower one to inform the software when the change is completed.
Note: Users cannot modify MDIV and CSS at the same access. Each field must be modified separately with a wait
for the MCKRDY flag between the first field modification and the second field modification.
31.5 Processor Clock Controller
The PMC features a Processor Clock (HCLK) Controller that implements the processor Sleep mode. HCLK can be
disabled by executing the WFI (W
aitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit
is at ‘0’ in the PMC Fast Startup Mode register (PMC_FSMR).
HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The processor Sleep mode is
entered by disabling HCLK, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset
of the product.
When processor Sleep mode is entered, the current instruction is finished before the clock is stopped, but this does
not prevent data transfers from other masters of the system bus.
31.6 SysTick External Clock
When the processor selects the SysTick external clock, the calibration value is fixed to 150000. This allows the
generation of a time base of 1 ms with the SysT
ick clock at the maximum frequency on HCLK divided by 2.
SAM E70/S70/V70/V71 Family
Power Management Controller (PMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 251