Datasheet

30.3 Block Diagram
Figure 30-1. Clock Generator Block Diagram
Power
Management
Controller
User Interface
Main Clock (MAINCK)
PLLA Clock (PLLACK)
ControlStatus
Main
Crystal
Oscillator
MOSCSEL
Clock Generator
PLLA and
Divider
Main RC
Oscillator
XIN
XOUT
XIN32
XOUT32
Slow Clock (SLCK)
SUPC_CR.XTALSEL
Slow RC
Oscillator
32.768 kHz
Crystal
Oscillator
UPLL Clock (UPLLCK)
USB UTMI
PLL
0
1
0
1
CKGR_MOR
CKGR_MOR.MOSCXTBY
SUPC_MR.OSCBYPASS
30.4 Slow Clock
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as
VDDIO is supplied, both the 32.768 kHz crystal oscillator and the Slow RC oscillator are powered, but only the Slow
RC oscillator is enabled. This allows the Slow clock (SLCK) to be valid in a short time (about 100
μs).
SLCK is generated either by the 32.768 kHz crystal oscillator or by the Slow RC oscillator.
To select the clock source, the selection is made via the XTALSEL bit in the Supply Controller Control Register
(SUPC_CR).
30.4.1 Slow RC Oscillator (32 kHz typical)
By default, the Slow RC oscillator is enabled and selected as a source of SLCK.
SAM E70/S70/V70/V71 Family
Clock Generator
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 243