Datasheet

30. Clock Generator

30.1 Description

The Clock Generator user interface is embedded within the Power Management Controller and is described in Power

Management Controller (PMC) User Interface. However

, the Clock Generator registers are named CKGR_.

30.2 Embedded Characteristics

The Clock Generator is comprised of the following:

• A low-power 32.768 kHz crystal oscillator with Bypass mode

• A low-power Slow RC oscillator (32 kHz typical)

• A 3 to 20 MHz Main crystal oscillator with Bypass mode

• A Main RC oscillator. Three output frequencies can be selected: 4/8/12 MHz. By default 12 MHz is selected. 8

MHz and 12 MHz are factory-trimmed.

• A 480 MHz UTMI PLL, providing a clock for the USB high-speed controller

• A 160 to 500 MHz programmable PLL (input from 8 to 32 MHz)

It provides the following clocks:

• SLCK — Slow clock. The only permanent clock within the system

• MAINCK — output of the Main clock oscillator selection: either the Main crystal oscillator or Main RC oscillator

• PLLACK — output of the divider and 160 to 500 MHz programmable PLL (PLLA)

• UPLLCK — output of the 480 MHz UTMI PLL (UPLL)

SAM E70/S70/V70/V71 Family

Clock Generator

echnology Inc.

Datasheet

DS60001527D-page 242