Datasheet

27.6.8 RTC Status Clear Command Register
Name: RTC_SCCR
Offset: 0x1C
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR
Access
W W W W W W
Reset – – – – – –
Bit 5 – TDERRCLR T
ime and/or Date Free Running Error Clear
Value Description
0
No effect.
1
Clears corresponding status flag in the Status Register (RTC_SR).
Bit 4 – CALCLR Calendar Clear
Value Description
0
No effect.
1
Clears corresponding status flag in the Status Register (RTC_SR).
Bit 3 – TIMCLR T
ime Clear
Value Description
0
No effect.
1
Clears corresponding status flag in the Status Register (RTC_SR).
Bit 2 – SECCLR Second Clear
Value Description
0
No effect.
1
Clears corresponding status flag in the Status Register (RTC_SR).
Bit 1 – ALRCLR Alarm Clear
Value Description
0
No effect.
1
Clears corresponding status flag in the Status Register (RTC_SR).
Bit 0 – ACKCLR Acknowledge Clear
Value Description
0
No effect.
1
Clears corresponding status flag in the Status Register (RTC_SR).
SAM E70/S70/V70/V71 Family
Real-time Clock (RTC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 225