Datasheet

27.6.7 RTC Status Register
Name: RTC_SR
Offset: 0x18
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
TDERR CALEV TIMEV SEC ALARM ACKUPD
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 5 – TDERR T
ime and/or Date Free Running Error
Value Name Description
0
CORRECT The internal free running counters are carrying valid values since the last read of the
Status Register (R
TC_SR).
1
ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-
BCD values) since the last read and/or they are still invalid.
Bit 4 – CALEV Calendar Event
The calendar event is selected in the CALEVSEL field in the Control Register (R
TC_CR) and can be any one of the
following events: week change, month change and year change.
Value Name Description
0
NO_CALEVENT No calendar event has occurred since the last clear.
1
CALEVENT At least one calendar event has occurred since the last clear.
Bit 3 – TIMEV T
ime Event
The time event is selected in the TIMEVSEL field in the Control Register (RTC_CR) and can be any one of the
following events: minute change, hour change, noon, midnight (day change).
Value Name Description
0
NO_TIMEVENT No time event has occurred since the last clear.
1
TIMEVENT At least one time event has occurred since the last clear.
Bit 2 – SEC Second Event
Value Name Description
0
NO_SECEVENT No second event has occurred since the last clear.
1
SECEVENT At least one second event has occurred since the last clear.
Bit 1 – ALARM Alarm Flag
Value Name Description
0
NO_ALARMEVENT No alarm matching condition occurred.
SAM E70/S70/V70/V71 Family
Real-time Clock (RTC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 223