Datasheet

The timing sequence of the time/calendar update is described in the figure below.

When entering the programming mode of the calendar fields, the time fields remain enabled and both the time and

the calendar fields are stopped. This is due to the location of the calendar logical circuity (downstream for low-power

considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode.

In successive update operations, the user must wait for at least one second after resetting the UPDTIM/UPDCAL bit

in the R

TC_CR before setting these bits again. This is done by waiting for the SEC flag in the RTC_SR before setting

the UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared.

Figure 27-2. Time/Calendar Update Timing Diagram

(counter stopped)

Clear

ACKUPD bit

Update request

from SW

Clear

UPDTIM bit

Update

RTC_TIMR.SEC to 15

Sofware

Time Line

2 43

RTC_SR.ACKUPD

SEC Event Flag

RTC_CR.UPDTIM

RTC_TIMR.SEC

1Hz RTC Clock

RTC BACK TO

NORMAL MODE

////

SAM E70/S70/V70/V71 Family

Real-time Clock (RTC)

echnology Inc.

Datasheet

DS60001527D-page 206