Datasheet

26.4.5.3 RSTC Mode Register
Name: RSTC_MR
Offset: 0x08
Reset: 0x00000001
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register
(SYSC_WPMR).
Bit 31 30 29 28 27 26 25 24
KEY[7:0]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
ERSTL[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
URSTIEN URSTEN
Access
R/W R/W
Reset 0 1
Bits 31:24 – KEY[7:0] W
rite Access Password
Value Name Description
0xA5
PASSWD Writing any other value in this field aborts the write operation. Always reads as 0.
Bits 11:8 – ERSTL[3:0] External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2
(ERSTL+1)
SLCK cycles.
This allows assertion duration to be programmed between 60
μs and 2 seconds. Note that synchronization cycles
must also be considered when calculating the actual reset length as previously described.
Bit 4 – URSTIEN User Reset Interrupt Enable
Value Description
0
RSTC_SR.USRTS at ‘1’ has no effect on the RSTC interrupt line.
1
RSTC_SR.USRTS at ‘1’ asserts the RSTC interrupt line if URSTEN = 0.
Bit 0 – URSTEN User Reset Enable
Value Description
0
The detection of a low level on the NRST pin does not generate a user reset.
1
The detection of a low level on the NRST pin triggers a user reset.
SAM E70/S70/V70/V71 Family
Reset Controller (RSTC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 202