Datasheet

...........continued
Date Changes
Section 40. “Quad SPI Interface (QSPI)”
Section 40.5.4 “Direct Memory Access Controller (DMA)”: added Note on 32-bit aligned DMA write
accesses.
Figure 40-9 “Instruction T
ransmission Flow Diagram”: modified text if TFRTYP = 0
Section 40.6.7 “Register Write Protection”: added Scrambling Mode Register and Scrambling Key
Register to the list of registers that can be write-protected.
Section 40.7.13 “QSPI Scrambling Mode Register” and Section 40.7.14 “QSPI Scrambling Key
Register”: added “This register can only be written if bit WPEN is cleared in the QSPI Write Protection
Mode Register.”.
Section 42. “Two-wire Interface (TWIHS)”
Replaced all instances of ‘BTC’ with ‘DMA status flag’.
Section 46. “MediaLB (MLB)”
Table 46-2 “MLB External Signals”: modified signal names in this table and throughout the section.
Section 47. “Controller Area Network (MCAN)”
Figure 47-1 “MCAN Block Diagram”: added Note.
Section 47.4.2 “Power Management”: added recommendations for CAN clock frequency.
Added Section 47.4.4 “Address Configuration”.
Section 48. “Timer Counter (TC)”
Replaced occurrences of ‘quadrature decoder logic’with ‘quadrature decoder’ or ‘QDEC’ throughout the
document.
Section 48.7.14 “TC Extended Mode Register”: changed description for field TRIGSRCB for value 1.
Section 49. “Pulse Width Modulation Controller (PWM)”
Section 49.5.3 “Interrupt Sources”: removed the following sentence: “Note that it is not recommended to
use the PWM interrupt line in Edge-sensitive mode.”
“Method 3: Automatic write of duty-cycle values and automatic trigger of the update”: removed
reference to non-existant field BTC.
Modified Figure 49-28 “External PWM Reset Mode: Power Factor Correction Application”.
Removed R
LIMIT
and Zener diode from Figure 49-32 “Cycle-By-Cycle Duty Mode: LED String Control”.
Section 50. “Analog Front-End Controller (AFEC)”
In text and tables throughout this section, all occurrences of ADVREF have been modified to VREFP
.
Figure 50-1, “Analog Front-End Controller Block Diagram”: added 2nd DAC. Removed ADVREF; added
VREFP and VREFN.
Table 50-1 “AFEC Signal Description”: removed row with VDDANA. Added row with VREFN.
Section 50.5 “Product Dependencies”: reorganized sub-sections. In Section 50.5.2 “Power
Management”, added sentence on Sleep mode. Modified Section 50.5.1 “I/O Lines”. Removed section
50.5.3 Analog Inputs.
Section 50.6.1 “Analog Front-End Conversion”: changed PRESCAL condition from ‘0’ to ‘1’ for
frequency range fperipheral clock/2.
Figure 50-7 “Analog Full Scale Ranges in Single-Ended/Differential Applications Versus Gain”: replaced
all occurrences of VADVREF with VVREFP; replaced min ‘0’ value with VVREFN=0.
Section 50.7.2 “AFEC Mode Register”: modified PRESCAL description.
24-Feb-15 Section 51. “Digital-to-Analog Converter (DACC)”
SAM E70/S70/V70/V71 Family
Revision History
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1970