Datasheet

Figure 26-6. User Reset Timing Diagram
SLCK
Processor and
Peripherals Reset Line
NRST
(nrst_out)
MCK
Any
Frequency.
RSTTYP
XXX
Main RC
Oscillator
Active
Active
Inactive
Inactive
Any
Frequency.
Inactive
Inactive
NRST pin
Min = 2 SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2)
0x4 = User Reset
2 SLCK cycles
6 SLCK cycles
26.4.4 Reset State Priorities
The reset state manager manages the priorities among the different reset sources. The resets are listed in order of
priority as follows:
1.
General reset
2. Backup reset
3. Watchdog reset
4. Software reset
5. User reset
Specific cases are listed below:
• When in user reset:
– A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
– A software reset is impossible, since the processor reset is being activated.
• When in software reset:
– A watchdog event has priority over the current state.
– The NRST has no effect.
• When in watchdog reset:
– The processor reset is active and so a software reset cannot be programmed.
– A user reset cannot be entered.
SAM E70/S70/V70/V71 Family
Reset Controller (RSTC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 197