Datasheet

...........continued
Date Changes
Section 18. “Bus Matrix (MATRIX)”
T
able 18-3 “Master to Slave Access”: changed Master 4/Slave 4 access from possible (“x”) to not
possble (‘-”)
Table 18-4 “Register Mapping”: changed reset value for CCFG_SYSIO register.
Section 18.12.7 “System I/O and CAN1 Configuration Register”: corrected typo in CAN1DMABA bit
name.
Section 18.11 “Register Write Protection”: replaced “The WPVS bit is automatically cleared after
reading the MATRIX_WPSR” with “The WPVS flag is reset by writing the MATRIX_WPMR with the
appropriate access key WPKEY”
Section 18.12.10 “Write Protection Status Register”: in WPVS bit description, replaced two instances of
“since the last read of the MATRIX_WPSR” with “since the last write of the MATRIX_WPMR”.
Section 21. “Enhanced Embedded Flash Controller (EEFC)”
Section 21.4.3.2 “Write Commands”: added information on DMA write accesses.
Section 30. “Power Management Controller (PMC)”
Section 30.9 “Asynchronous Partial Wake-up”: inserted new sub-section “Asynchronous Partial Wake-
up in Wait Mode (SleepWalking)” to better describe SleepWalking.
Section 30.10 “Free-Running Processor Clock”: removed reference to MCK.
Section 31. “Parallel Input/Output Controller (PIO)”
Section 31.2 “Embedded Characteristics”: added bullet on Programmable I/O Drive.
Added Section 31.5.12 “Programmable I/O Drive”.
Section 31.5.15.4 “Programming Sequence”: “With DMA”: in fifth step, replaced reference to BTCx with
‘DMA status flag to indicate that the buffer transfer is complete’
Table 31-5 “Register Mapping”: added PIO_DRIVER register at offset 0x0118 and added Section
31.6.49 “PIO I/O Drive Register”.
Section 35. “DMA Controller (XDMAC)”
Added Section 35.3 “DMA Controller Peripheral Connections”.
Section 37. “USB High-Speed Interface (USBHS)”
Table 37-1 “Description of USB Pipes/Endpoints“; corrected data in columns ‘DMA’ and ‘High
Bandwidth’.
Modified signal names to HSDM/DM and HSDP/DP in Figure 37-1 “USBHS Block Diagram” and Table
37-2 “Signal Description”. Updated descriptions.
Removed Section 37.3.1 “Application Block Diagram” and Figures 37-2, 37-3 and 37-4.
Removed Section 37.4.1 “I/O Lines”.
Modified Section 37.5.3.3 “Device Detection”.
Section 37.6.2 “General Status Register”, Section 37.6.3 “General Status Clear Register”, Section
37.6.4 “General Status Set Register”: removed bit VBUSRQ and bit description. Bit 9 now reserved in
these registers.
24-Feb-15 Section 38. “Ethernet MAC (GMAC)”
Section 38.8.13 “GMAC Interrupt Mask Register”: corrected general bit description (swapped definitions
provided for 0: and 1:)
SAM E70/S70/V70/V71 Family
Revision History
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1969