Datasheet
...........continued
Date Changes
Section 52. “Analog Front-End Controller (AFEC)”
Updated Section 52.6 “Functional Description”.
Section 52.6.1
1 “Input Gain and Offset” changed AOFF configuration value. Corrected formula for offset
values.
Updated Section 52.6.12 “AFE Timings”.
Section 52.6.18 “Register Write Protection”: added “AFEC Channel Differential Register” to the list of
write-protected registers.
Section 52.7.5 “AFEC Channel Sequence 2 Register”: corrected number of channels to 12.
Section 52.7.13 “AFEC Interrupt Status Register”: defined EOCAL bit as ‘cleared on read’.
Added sentence on write protection below the register table for:
Section 52.7.20 “AFEC Channel Offset Compensation Register”
Section 52.7.21 “AFEC Temperature Sensor Mode Register”
Section 52.7.25 “AFEC Correction Select Register”
Section 52.7.26 “AFEC Correction Values Register”
Section 52.7.27 “AFEC Channel Error Correction Register”
Section 52.7.20 “AFEC Channel Offset Compensation Register”: AOFF field modified to 10 bits (was 12
bits). Bits 10 and 11 now reserved.
08-Feb-16 Section 53. “Digital-to-Analog Converter Controller (DACC)”
External Trigger mode changed to Trigger mode throughout.
Removed references to ‘pipelined architecture’ and ‘pipeline’ throughout.
Added information on Bypass mode in:
- Section 53.1 “Description”
- Section 53.6.4.4 “Bypass Mode”
Updated Figure 53-1, “Block Diagram”.
Updated Section 53.6.1 “Digital-to-Analog Conversion”. Added sentence on DACRDY. Changed
‘maximum conversion rate’ to ‘minimum conversion period’.
Added Figure 53-2, “Conversion Sequence in Trigger Mode”and Figure 53-3, “Conversion Sequence in
Free-running Mode”.
Section 53.6.4.1 “Trigger Mode”: removed fragment ‘(either DATRG pin or timer counter events)’.
Section 53.6.4.2 “Free-Running Mode”: added sentence on FIFO.
Updated Figure 53-3, “Conversion Sequence in Free-running Mode”.
Updated Section 53.6.4.3 “Max Speed Mode” and added Figure 53-4, “Conversion Sequence in Max
Speed Mode”.
Updated Section 53.6.4.4 “Bypass Mode”.
Deleted section “DACC Timings”.
Table 53-4 “Register Mapping”: modified reset value for DACC_MR.
Section 53.7.2 “DACC Mode Register”: added bit ZERO (bit 5) and bit description.
Section 53.7.3 “DACC Trigger Register”: bit description changed for TRGSEL bit.
SAM E70/S70/V70/V71 Family
Revision History
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1966