Datasheet

...........continued
Date Changes
Section 46.7.17 “USART Channel Status Register”: added bits ITER, NACK, RIIC, DSRIC, DCDIC,
DSR, and DCD.
Section 46.7.23 “USAR
T Baud Rate Generator Register”: updated CD field description.
Added Section 46.7.27 “USART FI DI RATIO Register” and Section 46.7.29 “USART Number of Errors
Register”.
Section 49. “Controller Area Network (MCAN)”
Replaced ‘HCLK’ and ‘m_can_hclk’ by ‘peripheral clock’. Replaced ’can_clk’ by ‘CAN core clock’.
Replaced ‘tcan_clk’ by ‘tcore clock’.
Section 49.4.2 “Power Management”: added recommendations on clock frequencies.
Section 49.5.7 “Message RAM”: deleted sentence on storage constraints.
Section 49.5.7.5 “Standard Message ID Filter Element”: updated description of SFID2[5:0].
Section 49.5.7.6 “Extended Message ID Filter Element”: updated description of EFID2[5:0].
Added Section 49.6.1 “MCAN Core Release Register” and Section 49.6.2 “MCAN Endian Register” and
updated Table 49-13 “Register Mapping“.
Section 49.6.4 “MCAN Fast Bit Timing and Prescaler Register”: updated FSJW, FTSEG2 and FSTEG1
field description: t
core clock
now t
q
Section 49.6.8 “MCAN Bit Timing and Prescaler Register”: updated SJW, TSEG2, TSEG1 and BRP
field descriptions: t
core clock
now t
q
Section 50. “Timer Counter (TC)”
Added important note in Section 50.7.6 “TC Counter Value Register”, Section 50.7.7 “TC Register A”,
Section 50.7.8 “TC Register B” and Section 50.7.9 “TC Register C”.
Section 50.7.14 “TC Extended Mode Register”: updated TRIGSRCB bit description.
08-Feb-16 Section 51. “Pulse Width Modulation Controller (PWM)”
Number of fault inputs corrected to 8.
Size of dead-time counter/generator corrected to 12 bits.
Number of event lines corrected to 2.
Number of comparison units corrected to 8.
Updated Figure 51-1, “Pulse Width Modulation Controller Block Diagram”.
Updated Section 51.6.2.2 “Comparator”.
Updated Figure 51-33, “Leading-Edge Blanking”.
Section 51.6.6.1 “Initialization”: modified “Enable of the interrupts...” list item.
Added Section 51.6.6.4 “Changing the Update Period of Synchronous Channels”, Section 51.6.6.5
“Changing the Comparison Value and the Comparison Configuration” and Section 51.6.6.6 “Interrupt
Sources”.
Added reference to Section 51.5.4 “Fault Inputs” in register descriptions.
Corrected PWM period formulas in Section 51.7.43 “PWM Channel Period Register”and Section
51.7.44 “PWM Channel Period Update Register”.
Section 51.7.49 “PWM External Trigger Register” and Section 51.7.50 “PWM Leading-Edge Blanking
Register”: corrected register index to 2.
Section 51.7.50 “PWM Leading-Edge Blanking Register”: updated LEBDELAY bit description.
SAM E70/S70/V70/V71 Family
Revision History
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1965