Datasheet

...........continued
Date Changes
Section 38. “USB High-Speed Interface (USBHS)”
T
able 38-1 “Description of USB Pipes/Endpoints”: corrected value in ‘High Bandwidth’ column for Pipe/
Endpoint 1.
Added Section 38.4.1 “I/O Lines”.
Updated Figure 38-2, “General States”.
Updated Section 38.5.3.3 “Device Detection” and added Note on VBUS supply.
Section 38.6.1 “General Control Register”: added bit 8, VBUSHWC.
Section 38.6.4 “General Status Set Register”: added bit 9, VBUSRQS.
Section 38.6.12 “Device Endpoint Register”: bit 9 changed from ‘reserved’ to EPEN9. Bit 25 changed
from ‘reserved’ to EPRST9.
Bits 10 and 11 now reserved in registers:
- Section 38.6.6 “Device Global Interrupt Status Register”
- Section 38.6.9 “Device Global Interrupt Mask Register”
- Section 38.6.10 “Device Global Interrupt Disable Register”
- Section 38.6.11 “Device Global Interrupt Enable Register”
- Section 38.6.32 “Host Global Interrupt Status Register”
- Section 38.6.35 “Host Global Interrupt Mask Register”
- Section 38.6.36 “Host Global Interrupt Disable Register”
- Section 38.6.37 “Host Global Interrupt Enable Register”
08-Feb-16 Section 39. “Ethernet MAC (GMAC)”
Updated Section 39.1 “Description”.
Section 39.5.2 “Power Management”: deleted reference to PMC_PCER.
Section 39.5.3 “Interrupt Sources”: deleted reference to ‘Advanced Interrupt Controller’. Replaced by
‘interrupt controller’. Added information on interrupt sources and priority queues.
Section 39.6.14 “IEEE 1588 Support”: Removed reference to ‘output pins’ in 2nd paragraph. Deleted
reference to GMAC_TSSx.
Section 39.6.15 “Time Stamp Unit” added information on GTSUCOMP signal in last paragraph.
Updated register index range for:
- Section 39.8.106 “GMAC Interrupt Status Register Priority Queue x”
- Section 39.8.107 “GMAC Transmit Buffer Queue Base Address Register Priority Queue x”
- Section 39.8.108 “GMAC Receive Buffer Queue Base Address Register Priority Queue x”
- Section 39.8.109 “GMAC Receive Buffer Size Register Priority Queue x”
- Section 39.8.115 “GMAC Interrupt Enable Register Priority Queue x”
- Section 39.8.116 “GMAC Interrupt Disable Register Priority Queue x”
- Section 39.8.117 “GMAC Interrupt Mask Register Priority Queue x”
Section 39.8.117 “GMAC Interrupt Mask Register Priority Queue x”: inverted bit value definitions (‘0’
means enabled, ‘1’ means disabled.
Section 41. “Serial Peripheral Interface (SPI)”
Section 41.8.1 “SPI Control Register”: added bits FIFODIS, FIFOEN, RXFCLR, TXFCLR and REQCLR.
SAM E70/S70/V70/V71 Family
Revision History
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1963