Datasheet

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Date Comments
Section 37. “Image Sensor Interface (ISI)”
Updated “12-bit Grayscale Mode” .
Section 37.6.1 “ISI Configuration 1 Register”: added bit GRA
YLE at index 5 and bit description.
Section 37.6.12 “ISI Interrupt Enable Register”, Section 37.6.13 “ISI Interrupt Disable Register”:
changed access from “Read/Write” to “Write-only”.
Section 37.6.14 “ISI Interrupt Mask Register”: changed access from “Read/Write” to “Read-only”.
Section 38. “USB High-Speed Interface (USBHS)”
Section 38.6.1 “General Control Register”: added bit UID at index 24 and bit description.
cont’d
01-June-16 Section 39. “Ethernet MAC (GMAC)”
Throughout: Number of queues increased to 6 (was 3).
Updated Section 39.5.3 “Interrupt Sources”: number of interrupt sources increased to 6 (was 3).
Table 39-1 “GMAC Connections in Different Modes”: added table Note on GTXCK.
Added Section 39.6.18 ”Energy-efficient Ethernet Support” and Section 39.6.20 ”LPI Operation in the
GMAC”.
Section 39.7.1.2 “Receive Buffer List” and Section 39.7.1.3 “Transmit Buffer List”: added note on
queue pointer intilaization at end of sections .
Table 39-17, “Register Mapping”: added registers at offsets 0x270 to 0x27C.
Section 39.8.1 ”GMAC Network Control Register”: added bit 19: TXLPIEN: Enable LPI Transmission
(was ‘reserved’). Added bit description.
Section 39.8.3 ”GMAC Network Status Register”: added bit 7: RXLPIS: LPI Indication (was ‘reserved’).
and bit description.
Added bit 27: RXLPISBC: Receive LPI indication Status Bit Change, and bit description and bit 29:
TSUTIMCOMP: TSU timer comparison interrupt, and bit description in
- Section 39.8.10 ”GMAC Interrupt Status Register”
- Section 39.8.11 ”GMAC Interrupt Enable Register”
- Section 39.8.12 ”GMAC Interrupt Disable Register”
- Section 39.8.13 ”GMAC Interrupt Mask Register”.
Section 39.8.13 ”GMAC Interrupt Mask Register”: added bit 26, SRI, and bit 28, WOL, and bit
descriptions.
Added following sections:
Section 39.8.106 ”GMAC Received LPI Transitions”
Section 39.8.107 ”GMAC Received LPI Time”
Section 39.8.108 ”GMAC Transmit LPI Transitions”
Section 39.8.109 ”GMAC Transmit LPI Time”
Section 39.8.111 “GMAC Transmit Buffer Queue Base Address Register Priority Queue x” and Section
39.8.112 “GMAC Receive Buffer Queue Base Address Register Priority Queue x”: changed sentence
on register initialization.
Section 40. “High Speed Multimedia Card Interface (HSMCI)”
Section 40.14.2 “HSMCI Mode Register”: modified CLKDIV field description.
SAM E70/S70/V70/V71 Family
Revision History
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echnology Inc.
Datasheet
DS60001527D-page 1954