Datasheet

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDT_MR.WDRSTEN is written to ‘1’, the W
atchdog Timer is always reset after a watchdog reset, and the Watchdog
is enabled by default and with a period set to a maximum.
When WDT_MR.WDRSTEN is written to ‘0’, the watchdog fault has no impact on the RSTC.
After a watchdog overflow occurs, the report on the RSTC_SR.RSTTYP may differ (either WDT_RST or USER_RST)
depending on the external components driving the NRST pin. For example, if the NRST line is driven through a
resistor and a capacitor (NRST pin debouncer), the reported value is USER_RST if the low to high transition is
greater than one SLCK cycle.
Figure 26-4. Watchdog Reset Timing Diagram
0x2 = Watchdog Reset
SLCK
Processor and
Peripherals
Reset Line
NRST
(nrst_out)
MCK
Any
Frequency.
RSTTYP
XXX
Main RC
Oscillator
3 SLCK cycles + 2 MCK cycles
Active
Active
Inactive
Inactive
Any
Frequency.
Inactive
Inactive
WDT Fault
Min = 2 SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2)
26.4.3.4 Software Reset
The RSTC offers commands to assert the different reset signals. These commands are performed by writing the
Control register (RSTC_CR) with the following bits at ‘1’:
•
RSTC_CR.PROCRST: Writing a ‘1’ to PROCRST resets the processor and all the embedded peripherals,
including the memory system and, in particular, the Remap Command.
• RSTC_CR.EXTRST: Writing a ‘1’ to EXTRST asserts low the NRST pin during a time defined by the field
RSTC_MR.ERSTL.
The software reset is entered if at least one of these bits is written to ‘1’ by the software. All these commands can be
performed independently or simultaneously. The software reset lasts three SLCK cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset has ended, i.e., synchronously to SLCK.
If EXTRST is written to ‘1’, the nrst_out signal is asserted depending on the configuration of RSTC_MR.ERSTL.
However, the resulting falling edge on NRST does not lead to a user reset.
If and only if the RSTC_CR.PROCRST is written to ‘1’, the RSTC reports the software status in field
RSTC_SR.RSTTYP. Other software resets are not reported in RSTTYP.
As soon as a software operation is detected, RSTC_SR.SRCMP is written to ‘1’. SRCMP is cleared at the end of the
software reset. No other software reset can be performed while SRCMP is written to ‘1’, and writing any value in the
RSTC_CR has no effect.
SAM E70/S70/V70/V71 Family
Reset Controller (RSTC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 195