Datasheet

...........continued
Date Changes
Restructured Section 1. ”Description”.
Table 2-1 “Configuration Summary” : Added Note (3) on USART/UART functionality. Reorganized table
notes.
Table 6-3 “64-lead LQFP Package Pinout” : deleted signal names for pins 50, 51, 53 and 54 for PIO
Peripheral D. (now unassigned)
Table 14-1 “Peripheral Identifiers” : TWIHS0/1 instances read now as I2C-compatible.
Section 15. ”ARM Cortex-M7”
Number of IRQs changed to 74 in T
able 15-3 “ARM Cortex-M7 Configuration” and Section
15.4.6.3 ”Interrupt Program Status Register”.
Section 23. ”Supply Controller (SUPC)”
Section 23.4.10 ”Register Write Protection”: in list of protectable registers, removed “System Controller
Write Protection Mode Register”.
Section 24. ”Watchdog Timer (WDT)”
Removed references to LOCKMR in Section 24.4 ”Functional Description”, Section 24.5.1 ”Watchdog
Timer Control Register” and Section 24.5.2 ”Watchdog Timer Mode Register”.
Section 24.5.2 ”Watchdog Timer Mode Register”: corrected access to ‘Read/Write Once’.
Section 27. ”Real-time Clock (RTC)”
Reworked Positive Correction section in Figure 27-5 “Calibration Circuitry Waveforms”.
Section 30. ”Clock Generator”
Updated Section 30.5.2 ”Main RC Oscillator Frequency Adjustment”
Section 31. ”Power Management Controller (PMC)”
Figure 31-1 “General Clock Distribution Block Diagram”: updated PMC_PCR block.
Section 31.4 ”Master Clock Controller”: added note concerning fields MDIV and CSS.
“Core and Bus Independent Clocks for Peripherals” now Section 31.8 (was Section 32.12).
Table 31-1 “Clock Assignments” : added note on PCKx requirements.
Section 31.9 ”Peripheral and Generic Clock Controller”: changed title (was “Peripheral Clock Controller”)
and updated content regarding generic clock.
Section 31.12 ”Programmable Clock Output Controller”: in second paragraph, modified range of
selectable Output Signal dividing values from “a power of 2 between 1 and 64” to “1 to 256”.
Section 31.17 ”Recommended Programming Sequence”: in Step 8, modified range of PCKx prescaler
selectable values from “1, 2, 4, 8, 16, 32, 64” to “1 to 256”.
Table 31-4 “Register Mapping” : defined 0x0040_4040 as PMC_OCR reset value; deleted footnote “The
reset value depends on factory settings.”
Section 31.20.1 ”PMC System Clock Enable Register”, Section 31.20.2 ”PMC System Clock Disable
Register” and Section 31.20.3 ”PMC System Clock Status Register”: bit 15 modified to PCK7 (was
‘reserved’).
Section 31.20.10 ”PMC Clock Generator PLLA Register”: changed DIVA description for value ‘0’.
cont’d on next page
12-Oct-16 Section 33. ”External Bus Interface (EBI)”
T
able 33-1 “EBI I/O Lines Description” : added Note (1) on SDCK.
SAM E70/S70/V70/V71 Family
Revision History
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1947