Datasheet

26.4 Functional Description
26.4.1 Overview
The RSTC is made up of an NRST manager and a reset state manager. It runs at SLCK frequency and generates the
following reset signals:
•
proc_nreset: Processor reset line (also resets the Watchdog Timer)
• periph_nreset: Affects the whole set of embedded peripherals
• nrst_out: Drives the NRST pin
Note: proc_nreset and periph_nreset are driven in the same way.
These reset signals are asserted by the RSTC, either on events generated by peripherals, events on the NRST pin,
or on a software action. The reset state manager controls the generation of reset signals and provides a signal to the
NRST manager when an assertion of the NRST pin is required.
The NRST manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
The RSTC Mode register (RSTC_MR), used to configure the RSTC, is powered with VDDIO, so that its configuration
is saved as long as VDDIO is on.
26.4.2 NRST Manager
The NRST manager samples the NRST input pin and drives this pin low when required by the reset state manager.
The figure below shows the block diagram of the NRST manager.
Figure 26-2. NRST Manager
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
Other
interrupt
sources
user_reset
RSTC
Interrupt line
26.4.2.1 NRST Signal or Interrupt
The NRST manager samples the NRST pin at SLCK speed. When the NRST line is low for more than three clock
cycles, a User Reset is reported to the reset state manager
. The NRST pin must be asserted for at least 1 SLCK
clock cycle to ensure execution of a user reset.
However, the NRST manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing a
‘0’ to RSTC_MR.URSTEN disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL in the RSTC Status Register (RSTC_SR). As
soon as the NRST pin is asserted, RSTC_SR. URSTS is written to ‘1’. This bit is cleared only when the RSTC_SR is
read.
The RSTC can also be programmed to generate an interrupt instead of generating a reset. To do so,
RSTC_MR.URSTIEN must be set.
26.4.2.2 NRST External Reset Control
The reset state manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out”
signal is driven low by the NRST manager for a time programmed by RSTC_MR.ERSTL. This assertion duration,
named External Reset Length, lasts 2
(ERSTL+1)
SLCK cycles. This gives the approximate duration of an assertion
between 60 μs and 2 seconds. Note that ERSTL at ‘0’ defines a two-cycle duration for the NRST pulse.
SAM E70/S70/V70/V71 Family
Reset Controller (RSTC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 193