Datasheet

Note:
1.
The following schematic shows an example of USB High Speed host connection. For more information, refer
to 39. USB High-Speed Interface (USBHS)
+5V
PIO (VBUS ENABLE)
HSDM
HSDP
VBG
GNDUTMI
1
4
2
3
10 pF
"A" Receptacle
1 = VBUS
2 = D-
3 = D+
4 = GND
Shell = Shield
5K62 ± 1%
2. The following schematic shows a typical USB High Speed device connection: For more information, refer to
39. USB High-Speed Interface (USBHS).
PIO (VBUS DETECT)
HSDM
HSDP
VBG
GNDUTMI
C
RPB
:1µF to 10µF
C
RPB
1
4
2
3
10 pF
"B" Receptacle
1 = VBUS
2 = D-
3 = D+
4 = GND
Shell = Shield
15k
22k
5K62 ± 1%
(1)
(1)
Note:
The values shown on the 22 kΩ and 15 kΩ resistors are only valid with 3.3V supplied PIOs.
60.2.9 Memory Controllers
Signal Name Recommended Pin Connection Description
External Bus Interface
D[15:0] Application dependent. Data Bus (D0 to D15)
All data lines are pullup inputs to VDDIO at reset.
A[23:0] Application dependent. Address Bus (A0 to A23)
All address lines pullup inputs to VDDIO at reset.
NWAIT Application dependent. External Wait Signal.
Pulled-up input (100 kOhm) to VDDIO at reset.
SAM E70/S70/V70/V71 Family
Schematic Checklist
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1921