Datasheet

Figure 59-27. Two-wire Serial Bus Timing
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
TWCK
TWD
t
r
59.13.1.13 GMAC Characteristics
59.13.1.13.1 Timing Conditions
Table 59-63. Load Capacitance on Data, Clock Pads
Supply C
L
Max. Min.
3.3V 20 pF 0 pF
59.13.1.13.2 Timing Constraints
The GMAC must be constrained so as to satisfy the timings of standards shown below and in 58.13.1.13.3 MII
Mode, in MAX corner
.
Table 59-64. GMAC Signals Relative to GMDC
Symbol Parameter Min Max Unit
GMAC
1
Setup for GMDIO from GMDC rising 10 – ns
GMAC
2
Hold for GMDIO from GMDC rising 10 –
GMAC
3
GMDIO toggling from GMDC falling 0
(1)
10
(1)
Note: 1. For GMAC output signals, min and max access time are defined. The min access time is the time between
the GMDC falling edge and the signal change. The max access timing is the time between the GMDC falling edge
and the signal stabilizes. The figure below illustrates min and max accesses for GMAC
3
.
Figure 59-28. Min and Max Access T
ime of GMAC Output Signals
GMDC
GMDIO
GMAC
3 max
GMAC
1
GMAC
2
GMAC
4
GMAC
5
GMAC
3 min
SAM E70/S70/V70/V71 Family
Electrical Characteristics for SAM E70/S70
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1903