Datasheet

Table 59-62. Two-wire Serial Bus Requirements
Symbol Parameter Condition Min. Max. Unit
V
IL
Low-level Input Voltage – -0.3 0.3 V
DDIO
V
V
IH
High-level Input Voltage – 0.7 × V
DDIO
V
CC
+ 0.3 V
V
hys
Hysteresis of Schmitt Trigger Inputs – 0.150 – V
V
OL
Low-level Output Voltage 3 mA sink current – 0.4 V
t
R
Rise Time for both TWD and TWCK 20 + 0.1C
b
(1)(2)
300 ns
t
OF
Output Fall Time from V
IHmin
to V
ILmax
10 pF < C
b
< 400 pF
see the figure below
20 + 0.1C
b
(1)(2)
250 ns
C
i
(1)
Capacitance for each I/O Pin – – 10 pF
f
TWCK
TWCK Clock Frequency – 0 400 kHz
R
P
Value of Pull-up resistor f
TWCK
≤ 100 kHz (V
DDIO
- 0.4V) ÷ 3mA 1000ns ÷ C
b
Ω
f
TWCK
> 100 kHz 300ns ÷ C
b
Ω
t
LOW
Low Period of the TWCK clock f
TWCK
≤ 100 kHz
(3)
– µs
f
TWCK
> 100 kHz
(3)
– μs
t
HIGH
High period of the TWCK clock f
TWCK
≤ 100 kHz
(4)
– μs
f
TWCK
> 100 kHz
(4)
– μs
t
HD;STA
Hold Time (repeated) START Condition f
TWCK
≤ 100 kHz t
HIGH
– μs
f
TWCK
> 100 kHz t
HIGH
– μs
t
SU;STA
Set-up time for a repeated START
condition
f
TWCK
≤ 100 kHz t
HIGH
– μs
f
TWCK
> 100 kHz t
HIGH
– μs
t
HD;DAT
Data hold time f
TWCK
≤ 100 kHz 0 3 × t
CPMCK
(5)
μs
f
TWCK
> 100 kHz 0 3 ×t
CPMCK
(5)
μs
t
SU;DAT
Data setup time f
TWCK
≤ 100 kHz t
LOW -
3 × t
CPMCK
(5)
– ns
f
TWCK
> 100 kHz t
LOW -
3 × t
CPMCK
(5)
– ns
t
SU;STO
Setup time for STOP condition f
TWCK
≤ 100 kHz t
HIGH
– μs
f
TWCK
> 100 kHz t
HIGH
– μs
t
HD;STA
Hold Time (repeated) START Condition f
TWCK
≤ 100 kHz t
HIGH
– μs
f
TWCK
> 100 kHz t
HIGH
– μs
Note:
1.
Required only for f
TWCK
> 100 kHz.
2. C
b
= capacitance of one bus line in pF. Per I
2
C standard, C
b
max = 400pF.
3. The TWCK low period is defined as follows: t
LOW
= ((CLDIV × 2
CKDIV
) + 4) × t
MCK
.
4. The TWCK high period is defined as follows: t
HIGH
= ((CHDIV × 2
CKDIV
) + 4) × t
MCK
.
5. t
CPMCK
= MCK bus period
SAM E70/S70/V70/V71 Family
Electrical Characteristics for SAM E70/S70
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1902