Datasheet

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Symbol Parameter Conditions Min Max Unit
QSPI
1
QIOx data in to QSCK rising edge (input hold time) 3.3V domain 0 – ns
1.8V domain 0 – ns
QSPI
2
QSCK rising edge to QIOx data out valid 3.3V domain -1.3 1.9 ns
1.8V domain -2.5 3.0 ns
QSPI
3
QIOx data in to QSCK falling edge (input setup time) 3.3V domain 2.9 – ns
1.8V domain 3.2 – ns
QSPI
4
QIOx data in to QSCK falling edge(input hold time) 3.3V domain 0 – ns
1.8V domain 0 – ns
QSPI
5
QSCK falling edge to QIOx data out valid 3.3V domain -1.6 1.8 ns
1.8V domain -2.7 3.1 ns
Timings are given for the 3.3V domain, with VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF.
59.13.1.6 SPI Characteristics
In the figures below, the MOSI line shifting edge is represented with a hold time equal to 0. However, it is important to
note that for this device, the MISO line is sampled prior to the MOSI line shifting edge. As shown further below
, the
device sampling point extends the propagation delay (t
p
) for slave and routing delays to more than half the SPI clock
period, whereas the common sampling point allows only less than half the SPI clock period.
As an example, an SPI Slave working in Mode 0 can be safely driven if the SPI Master is configured in Mode 0.
Figure 59-19. MISO Capture in Master Mode
MISO
(slave answer)
SPCK
(generated
by the master)
MISO cannot be provided
before the edge
Bit N Bit N+1
0 < delay < SPI0 or SPI3
Bit N
Internal
shift register
Safe margin,
always >0
Common sampling point
Device sampling point
t
p
Extended t
p
Figure 59-20. SPI Master Mode with (CPOL= NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
MISO
MOSI
SPI
2
SPI
0
SPI
1
SAM E70/S70/V70/V71 Family
Electrical Characteristics for SAM E70/S70
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1893