Datasheet

...........continued
Parameter Conditions Min. Typ. Max. Unit
Flash Active Current Random 128-bit read at maximum
frequency at 25°C
on V
DDCORE
=1.2V – 16 20 mA
on V
DDIO
– 2 10
Program at 25°C on V
DDCORE
=1.2V – 2 3
on V
DDIO
– 8 12
Erase at 25°C on V
DDCORE
=1.2V – 2 2
on V
DDIO
– 8 12
Note: 1. Cycling over full temperature range.
Maximum operating frequencies are shown in the following table, but are limited by the Embedded Flash access time
when the processor is fetching code out of it. These tables provide the device maximum operating frequency defined
by the field FWS of the EEFC_FMR register
. This field defines the number of wait states required to access the
Embedded Flash Memory.
Table 59-51. Embedded Flash Wait States for Worst-Case Conditions
FWS Read Operations
Maximum Operating Frequency (MHz)
VDDIO = 1.7V VDDIO = 3.0V
0 1 cycle 21 23
1 2 cycles 42 46
2 3 cycles 63 69
3 4 cycles 84 92
4 5 cycles 106 115
5 6 cycles 125 138
6 7 cycles 137 150
59.13 Timings for STH Conditions
59.13.1 AC Characteristics
59.13.1.1 Processor Clock Characteristics
Table 59-52. Processor Clock Waveform Parameters
Symbol Parameter Conditions Min. Max. Unit
1/(t
CPPCK
) Processor Clock Frequency Worst case – 300 MHz
59.13.1.2 Master Clock Characteristics
Table 59-53. Master Clock Waveform Parameters
Symbol Parameter Conditions Min Max Unit
1/(t
CPMCK
) Master Clock Frequency Worst case – 150 MHz
59.13.1.3 I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
SAM E70/S70/V70/V71 Family
Electrical Characteristics for SAM E70/S70
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1890