Datasheet

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Symbol Parameter Condition Min. Max. Unit
SSC
12
RF/RD hold time after RK edge (RK output) – t
CPMCK
- 2.8 – ns
SSC
13
RK edge to RF (RK output) – -2.1
(1)
1.9
(1)
ns
Note: For output signals (TF
, TD, RF), minimum and maximum access times are defined. The minimum access time
is the time between the TK (or RK) edge and the signal change. The maximum access timing is the time between the
TK edge and the signal stabilization. The figure below illustrates the minimum and maximum accesses for SSC0, and
the same is applicable for SSC1, SSC4, SSC7, SSC10, and SSC13.
Figure 58-41. Min and Max Access Time of Output Signals
TK (CKI =1)
TF/TD
SSC
0min
TK (CKI =0)
SSC
0max
58.13.1.15 ISI Timings
58.13.1.15.1 Timing Conditions
Timings are given assuming the load capacitance in the following table.
T
able 58-69. Load Capacitance
Supply C
L
Max
3.3V 30 pF
58.13.1.15.2 Timing Extraction
Table 58-70. ISI Timings with Peripheral Supply 3.3V
Symbol Parameter Min. Max. Unit
ISI
1
DATA/VSYNC/HSYNC setup time 1.5 – ns
ISI
2
DATA/VSYNC/HSYNC hold time -1.2 – ns
ISI
3
PIXCLK frequency – 75 MHz
Figure 58-42. ISI Timing Diagram
PIXCLK
DATA[7:0]
VSYNC
HSYNC
Valid Data
Valid Data Valid Data
1 2
3
SAM E70/S70/V70/V71 Family
Electrical Characteristics for SAM ...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1862