Datasheet

In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by setting

bit RSWDT_CR.WDRSTT

. The watchdog counter is then immediately reloaded from the RSWDT_MR and restarted,

and the slow clock 128 divider is reset and restarted. The RSWDT_CR is write-protected. As a result, writing

RSWDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to

the Reset Controller is asserted if RSWDT_MR.WDRSTEN is set. Moreover, WDUNF (Watchdog Underflow) is set in

the Status Register (RSWDT_SR).

The status bits WDUNF and WDERR trigger an interrupt, provided the WDFIEN bit is set in the RSWDT_MR. The

signal “wdt_fault” to the Reset Controller causes a Watchdog reset if the WDRSTEN bit. For details, refer to the

section “Reset Controller (RSTC)”. In this case, the processor and the RSWDT are reset, and the WDUNF and

WDERR flags are reset.

If a reset is generated, or if RSWDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault”

signal to the reset controller is deasserted

Writing RSWDT_MR reloads and restarts the down counter.

The RSWDT is disabled after any power-on sequence.

While the processor is in Debug state or in Idle mode, the counter may be stopped depending on the value

programmed for the WDIDLEHLT and WDDBGHLT bits in the RSWDT_MR.

Figure 25-2. Watchdog Behavior

WDV

RSWDT_CR.WDRSTT = 1

Watchdog

Fault

Normal behavior

Watchdog Underflow

0xFFF

if WDRSTEN is 1

if WDRSTEN is 0