Datasheet

57.5.10 AES Initialization Vector Register x
Name: AES_IVRx
Offset: 0x60 + x*0x04 [x=0..3]
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
IV[31:24]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
IV[23:16]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
IV[15:8]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
IV[7:0]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 –
Bits 31:0 – IV[31:0] Initialization V
ector
The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some
modes of operation as an additional initial input.
AES_IVR0 corresponds to the first word of the Initialization Vector, AES_IVR3 to the last one.
These registers are write-only to prevent the Initialization Vector from being read by another application.
For CBC, OFB and CFB modes, the IV input value corresponds to the initialization vector.
For CTR mode, the IV input value corresponds to the initial counter value.
Note: These registers are not used in ECB mode and must not be written.
SAM E70/S70/V70/V71 Family
Advanced Encryption Standard (AES)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1811