Datasheet

24.5.2 Watchdog Timer Mode Register
Name: WDT_MR
Offset: 0x04
Reset: 0x3FFF2FFF
Property: Read/Write Once
The first write access prevents any further modification of the value of this register. Read accesses remain possible.
The WDT_MR register values must not be modified within three slow clock periods following a restart of the
watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of
period earlier than expected.
Bit 31 30 29 28 27 26 25 24
WDIDLEHLT WDDBGHLT WDD[11:8]
Access
R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1
Bit 23 22 21 20 19 18 17 16
WDD[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8
WDDIS WDRSTEN WDFIEN WDV[11:8]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 0 1 1 1 1
Bit 7 6 5 4 3 2 1 0
WDV[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 29 – WDIDLEHLT W
atchdog Idle Halt
Value Description
0
The watchdog runs when the system is in idle state.
1
The watchdog stops when the system is in idle state.
Bit 28 – WDDBGHLT W
atchdog Debug Halt
Value Description
0
The watchdog runs when the processor is in debug state.
1
The watchdog stops when the processor is in debug state.
Bits 27:16 – WDD[11:0] W
atchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, setting bit WDT_CR.WDRSTT restarts the timer.
If the Watchdog Timer value is greater than WDD, setting bit WDT_CR.WDRSTT causes a watchdog error.
Bit 15 – WDDIS Watchdog Disable
When setting the WDDIS bit, and while it is set, the fields WDV and WDD must not be modified.
Value Description
0
Enables the Watchdog Timer.
1
Disables the Watchdog Timer.
Bit 13 – WDRSTEN W
atchdog Reset Enable
Value Description
0
A watchdog fault (underflow or error) has no effect on the resets.
SAM E70/S70/V70/V71 Family
W
atchdog Timer (WDT)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 181