Datasheet

57.5.3 AES Interrupt Enable Register
Name: AES_IER
Offset: 0x10
Reset: –
Property: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Enables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
TAGRDY
Access
W
Reset –
Bit 15 14 13 12 11 10 9 8
URAD
Access
W
Reset –
Bit 7 6 5 4 3 2 1 0
DATRDY
Access
W
Reset –
Bit 16 – TAGRDY GCM T
ag Ready Interrupt Enable
Bit 8 – URAD Unspecified Register Access Detection Interrupt Enable
Bit 0 – DATRDY Data Ready Interrupt Enable
SAM E70/S70/V70/V71 Family
Advanced Encryption Standard (AES)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1804