Datasheet

24.5.1 Watchdog Timer Control Register
Name: WDT_CR
Offset: 0x00
Reset: –
Property: Write-only
The WDT_CR register values must not be modified within three slow clock periods following a restart of the watchdog
performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier
than expected.
Bit 31 30 29 28 27 26 25 24
KEY[7:0]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 –
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
WDRSTT
Access
W
Reset –
Bits 31:24 – KEY[7:0] Password
Value Name Description
0xA5
PASSWD Writing any other value in this field aborts the write operation.
Bit 0 – WDRSTT W
atchdog Restart
Value Description
0
No effect.
1
Restarts the watchdog if KEY is written to 0xA5.
SAM E70/S70/V70/V71 Family
W
atchdog Timer (WDT)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 180