Datasheet

Note:
1.
In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in
processing.
2. In 32, 16, and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 is not allowed
and may lead to errors in processing.
57.4.6.2 Auto Mode
The Auto Mode is similar to the manual one, except that in this mode, as soon as the correct number of
AES_IDATARx is written, processing is automatically started without any action in AES_CR.
57.4.6.3 DMA Mode
The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer without
any action by software during processing.
AES_MR.SMOD must be configured to 2 and the DMA must be configured with non-incremental addresses.
The start address of any transfer descriptor must be configured with the address of AES_IDATAR0.
The DMA chunk size configuration depends on the AES mode of operation and is listed in the table below.
When writing data to AES with a first DMA channel, data are first fetched from a memory buffer (source data). It is
recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination
data size depends on the mode of operation. When reading data from the AES with the second DMA channel, the
source data is the data read from AES and data destination is the memory buffer. In this case, the source data size
depends on the AES mode of operation and is listed in the table below.
Table 57-3. DMA Data Transfer Type for the Different Operating Modes
Operating Mode Chunk Size Destination/Source Data Transfer Type
ECB 4 Word
CBC 4 Word
OFB 4 Word
CFB 128-bit 4 Word
CFB 64-bit 1 Word
CFB 32-bit 1 Word
CFB 16-bit 1 Half-word
CFB 8-bit 1 Byte
CTR 4 Word
GCM 4 Word
57.4.7 Security Features
57.4.7.1 Unspecified Register Access Detection
When an unspecified register access occurs, AES_ISR.URAD is raised. Its source is then reported in
AES_ISR.URA
T. Only the last unspecified register access is available through the AES_ISR.URAT.
Several kinds of unspecified register accesses can occur:
• Input Data register written during the data processing when SMOD = IDATAR0_START
• Output Data register read during data processing
• Mode register written during data processing
• Output Data register read during sub-keys generation
• Mode register written during sub-keys generation
• Write-only register read access
SAM E70/S70/V70/V71 Family
Advanced Encryption Standard (AES)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1796