Datasheet

To run a GF
128
multiplication (A x B), the sequence is as follows:
1. Set AES_MR.OPMOD to GCM and AES_MR.GT
AGEN to ‘0’.
1. Configure AES_AADLENR.AADLEN with 0x10 (16 bytes) and AES_CLENR.CLEN to ‘0’. This will allow
running a single GHASH
H
.
2. Fill AES_GCMHRx.H with B value.
3. Fill AES_IDATARx.IDATA with the A value according to the SMOD configuration used. If Manual Mode or Auto
Mode is used, the DATRDY bit indicates when a GHASHH computation is over (use interrupt if needed).
4. Read AES_GHASHRx.GHASH to obtain the result.
Note: AES_GHASHRx.GHASH can be initialized with a value C between step 3 and step 4 to run a ((A XOR C) x B)
GF
128
multiplication.
57.4.5 Double Input Buffer
AES_IDATARx can be double-buffered to reduce the runtime of large files.
This mode allows a new message block to be written when the previous message block is being processed. This is
only possible when DMA accesses are performed (AES_MR.SMOD = 2).
AES_MR.DUALBUFF must be set to ‘1’ to access the double buf
fer.
57.4.6 Start Modes
AES_MR.SMOD allows selection of the encryption (or decryption) Start mode.
57.4.6.1 Manual Mode
The sequence of actions is as follows:
1.
Write AES_MR with all required fields, including but not limited to SMOD and OPMOD.
2. Write the 128-bit/192-bit/256-bit AES key in AES_KEYWRx.
3. Write the initialization vector (or counter) in AES_IVRx.
Note: AES_IVRx concerns all modes except ECB.
4. Set the bit DATRDY (Data Ready) in the AES Interrupt Enable register (AES_IER), depending on whether an
interrupt is required or not at the end of processing.
5. Write the data to be encrypted/decrypted in the authorized AES_IDATARx (see the table below).
6. Set the START bit in the AES Control register (AES_CR) to begin the encryption or the decryption process.
7. When processing completes, the DATRDY flag in the AES Interrupt Status register (AES_ISR) is raised. If an
interrupt has been enabled by setting AES_IER.DATRDY, the interrupt line of the AES is activated.
8. When software reads one of AES_ODATARx, AES_IER.DATRDY is automatically cleared.
Table 57-2. Authorized Input Data Registers
Operating Mode Input Data Registers to Write
ECB All
CBC All
OFB All
128-bit CFB All
64-bit CFB AES_IDATAR0 and AES_IDATAR1
32-bit CFB AES_IDATAR0
16-bit CFB AES_IDATAR0
8-bit CFB AES_IDATAR0
CTR All
GCM All
SAM E70/S70/V70/V71 Family
Advanced Encryption Standard (AES)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1795