Datasheet

55.6.7 ICM Interrupt Status Register
Name: ICM_ISR
Offset: 0x1C
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
URAD
Access
R
Reset 0
Bit 23 22 21 20 19 18 17 16
RSU[3:0] REC[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RWC[3:0] RBE[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RDM[3:0] RHC[3:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 24 – URAD Undefined Register Access Detection Status
The URAD bit is only reset by the SWRST bit in ICM_CTRL.
The URA
T field in ICM_UASR indicates the unspecified access type.
Value Description
0
No undefined register access has been detected since the last SWRST.
1
At least one undefined register access has been detected since the last SWRST.
Bits 23:20 – RSU[3:0] Region Status Updated Detected
When RSU[i] is set, it indicates that a region status updated condition has been detected.
Bits 19:16 – REC[3:0]
Region End Bit Condition Detected
When REC[i] is set, it indicates that an end bit condition has been detected.
Bits 15:12 – RWC[3:0] Region Wrap Condition Detected
When RWC[i] is set, it indicates that a wrap condition has been detected.
Bits 11:8 – RBE[3:0] Region Bus Error
When RBE[i] is set, it indicates that a bus error has been detected while hashing memory region i.
Bits 7:4 – RDM[3:0] Region Digest Mismatch
When RDM[i] is set, it indicates that there is a digest comparison mismatch between the hash value of the region with
identifier i and the reference value located in the Hash Area.
Bits 3:0 – RHC[3:0] Region Hash Completed
When RHC[i] is set, it indicates that the ICM has completed the region with identifier i.
SAM E70/S70/V70/V71 Family
Integrity Check Monitor (ICM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1771