Datasheet

24. Watchdog Timer (WDT)
24.1 Description
The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It
features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can
generate a general reset or a processor reset only
. In addition, it can be stopped while the processor is in Debug
mode or Sleep mode (Idle mode).
24.2 Embedded Characteristics
• 12-bit Key-protected Programmable Counter
•
Watchdog Clock is Independent from Processor Clock
• Provides Reset or Interrupt Signals to the System
• Counter May Be Stopped while the Processor is in Debug State or in Idle Mode
24.3 Block Diagram
Figure 24-1. Watchdog Timer Block Diagram
= 0
10
set
reset
read WDT_SR
or
reset
wdt_fault
(to Reset Controller)
set
reset
WDFIEN
wdt_int
WDT_MR
SLCK
1/128
12-bit Down
Counter
Current
Value
WDD
WDT_MR
<= WDD
WDV
WDRSTT
WDT_MR
WDT_CR
reload
WDUNF
WDERR
reload
write WDT_MR
WDT_MR
WDRSTEN
SAM E70/S70/V70/V71 Family
W
atchdog Timer (WDT)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 176